On-Line FPAA Workshop

Goal : Provide an On-line FPAA Workshop Course enabling anyone with access to an FPAA board compatible with the SoC FPAA device family

History : FPAA device development has been tightly linked with education of users not involved in that original FPAA design. The ICE (Integrated Computational Electronics) Laboratory from Georgia Tech (GT) developed and evolved a number of FPAA workshops. The initial concepts for these workshops started from educational approaches at GT in analog and neurmorphic circuits, where many of thes approaches build upon the Analog VLSI and Neural Systems (CNS 182) course at Caltech. The first dedicated FPAA workshop session was held at USC in May 2008. Since 2008 this group has averaged one to two workshops a year. As of August 2019, hundreds of individuals have participated in an FPAA workshop in some form.

Typically the workshops were a combination of lectures, hands-on experiments using the FPAA boards, and a range of technical discussions around these experiments. We alternated the lectures and experiments to maximize the energy, learning, and resulting discussions. Some workshops often took a life of their own depending on the particular individuals and particular interests of those individuals. Even so, most workshops eventually converged on a particular core set of topics almost always covered, and we use that experience in building this set of curricular material.

Approach : We will continue to teach FPAA device utilization and develop new FPAA workshops. The following sections are designed to help get individuals to use the FPAA boards, ideally independantly of anyone else being part of the learning process. We learn a significant amount with every workshop We strive to enabling others to use these FPAA devices. This effort becomes the starting point for learning this material to come up to speed and have questions for dedicated help sessions, or the starting point (questions, first hour of a meeting) for more advanced workshop sessions

Section I : Physical Computing Overview ( .pdf slides )

  • Perceptions on Analog and Digital Computing and FPAA opportunities
  • Why Analog / Physical Computing? Energy and area efficicency as well as negligable latency
  • Theoretical Infrastructure for Digital and Analog (Physical) Computation

Section II : Overview of FPAA Devices ( .pdf slides )

Section III : Starting Experimental Session, Low Pass Filter (LPF) ( .pdf slides )

Section IV : BandPass Filter (BPF) ( .pdf slides )

Section V : Hodgkin-Huxley Biological Neuron Modeling and Computation ( .pdf slides )

  • Setting up transistor biological channel model
  • Biological Transistor Model
  • Converting Classical Channel Model to FPAA Implementation
  • HH Tool example for SoC FPAA
  • HH Experimental Session: Measurement of HH Channel Transistor Model
  • Background papers:
    • Channel Neuron on an SoC FPAA:
    • Synapses + Channel Neuron on an SoC FPAA: .pdf

Section VI : VMM + WTA classifier structure ( .pdf slides )

  • Experimental Session: VMM+WTA classifier for XOR function

Additional Resources : SoC FPAA Papers and Materials

  • SoC FPAA device, circuit, system, and tools site
  • A couple of academic papers were written on the approach used in teaching classes at GT that paralleled our efforts for these workshops. FPAA devices in the classroom + SoC FPAA board design , graduate course initial assessment, FPAA devices in Junior-level Circuits Course ( pdf ), and its implications for circuit design and education ( pdf )).

Eventually, full papers on the history and pedogodgy of these workshops will appear.

Overview Videos:

  • FPAA Enabling Physical Computing: Video
  • FPAA: History, Development, Classification, and Directions: Video
  • Historical Introduction to Floating-Gate (FG) Circuits: Video
  • Starting point on standard-cell libraries: Video