Class Schedule

Projects will consist of analytical problems, design problems, as well as our final design project. Lectures will closely correspond to the projects that we are working on that week.

Topic Date
Project #1: MOSFET device modeling & SPICE & layout parasitics Sept 11
Project #2: MOSFET Transistor Circuits and Transconductance Amplifiers Oct 3
Project #3: Stability, programmability, references, and further amplifier design Nov 6
Project #4: Analog System Design Dec 10 (Final Exam day?)

First Day of Class August 23
Days off: Fall Break (Oct 5,6), Nov. 25-27
Last Day of Normal Classs: Dec. 3 (Dead days: Dec 7,8)

Open-Source Global Foundries 180nm CMOS Tools: are required for this class. The great thing about this opportunity is everything is openly available, as well as there is a community that can openly talk about this material. Most IC design processes do not give these options.

The core tools are embedded in an Ubuntu virtual machine, and is supported for both Windows and MAC M-series machines:

  • For Windows and Intel MAC machines, download the zip file ECE4430_WinVM.zip, and for Mac M-series machines download the zip file ECE4430_MacVM.utm.zip, both available in this link: OpenSourcePDKs_VM_GF180
  • For Windows and Intel MAC machines, download the Virtual box application and import the file downloaded in previous step.
  • For Mac M-series machines, download the UTM application and import the file downloaded in previous step.
  • Username and Password information:
    • For Windows and Intel MAC VM: username: icelab password: icelab
    • For Mac M-series VM: username: ece4430 password: ece4430
  • Commands to open tools:
    • For Schematic Capture (Xschem): xschem-gf
    • For Layout (option 1 -> Magic): magic-gf
    • For Layout (option 2 -> Klayout): klayout-gf
    • For LVS Checks: first, install Netgen using the command sudo apt install netgen-lvs. To run Netgen on your spice files, run the command:
      netgen-lvs lvs ~/location_to_spice_file/magic_file.spice ~/location_to_spice_file/xschem_file.spice ~/pdks/gf180mcuD/ libs.tech/netgen/gf180mcuD_setup.tcl
      To obtain spice netlists for your Magic layout, use the following commands in the console after finishing your design:
      extract all ext2spice -d ext2spice lvs
      To obtain spice netlists for your Xschem design, you must first enable the option "LVS netlist + Top level is a .subckt" located in the Simulation > LVS tab. From there, simply press the netlist button.

Open-Source Skywater 130nm CMOS Tools: are required for this class. The great thing about this opportunity is everything is openly available, as well as there is a community that can openly talk about this material. Most IC design processes do not give these options.

The core tools are embedded in an Ubuntu 20.04 virtual machine: .ova file

  • The .ova file (we use VirtualBox) is large (>10GB), so you might want to plan accordingly.
  • The main user account name is hilas.
  • The system has the required tools for the skywater submission, and includes a set of analog standard-cell elements that might be useful.
  • You likely will want to add a shared folder so you have easy access to your VM from your host machine.
  • To start magic from a particular directory, use the command
    magic -T ~/fastlane/pdks/sky130A_hilas/libs.tech/magic/sky130A.tech &
  • Initally can run Xschem (circuit schematics) from ~.xschem/xschemSky130 with the command xschem.
  • The VM (unintentionally) does not have a spice simulator included in the VM. My recommendation would be to use ngspice (download), effectively a port of the original Berkeley Spice (3F5). The spice extracted output from Xschem can be simulated directly by ngspice after you ahve included your EKV spice model files You make your spice model file in the first project from measured data).
    To download ngspice in the VM, you should be able to run the command
    "sudo apt install ngspice"
    In future VM versions, we will include this tool already set up. The ngspice manual has alot of the important details.

If you want to make your own setup, Praveen Raj provides some information that is in a file, and potentially updated GITHUB. The class is not supporting this development, but this material is provided as it might be helpful.

A few useful additional links:

  • General essay on Skywater CMOS 130nm Technology and Open-Source IC fabrication.
  • Skywater Process Available Devices
  • Skywater Layer Stack
  • Skywater 130nm Process Design Rules Rules
  • Magic IC Design Tools

Previous semesters used the Cadence tools. For legacy discussions, I have kept a few useful links:

  • One Cadence Setup Handout used in previous ECE 4430 Class (different IC process).
  • Georgia Tech Cadence page
  • Georgia Tech NCSU software page
  • NCSU kit documentation page
  • Page for NCSU techfile The tsmc_02 tech file corresponds to the Cadence 180nm CMOS process. The file might slightly change, and such instructions will be discussed in class.

Example Problems that were used when I had an exam for this class, and you can review the exam I gave in Fall 2017, 2019, and additional example problems (not to be turned in)

FPAA starting materials : Although the large-scale Field Programmable Analog Arrays (FPAA) are not central to this course, you might find the information helpful at times this semester, and therefore we provide some FPAA starting materials.