Biological Passive and Active Channel Models

Course Materials

Taped Lectures

Reading Material

Summary Notes (.html format)

Project Approach

This project focuses on understanding and experimentally measuring the transistor channel model approach for handling passive and active channels. At the end of this project, you will build your own block. This project is so critical for understanding that everyone will do exactly the same project.

In the examples pull-down for your FPAA tools is an HH Neuron experiment, entirely using internal FPAA concepts. You should start with this neuron, and its dynamics. You will want to tune this neuron, since there will be some mismatch due to indirect programming, which is not adjusted for this particular demonstration. In all cases, the demonstration should work and give functional results to enable tuning.

Remember, there is an hhneuron blocks (instrumented and uninstrumented). The uninstrumented block (which is used in the example file), hhneuron block is in palette under FPAA. It has inputs Vin, ENa, EK, Vref (dc bias for Na gating) and outputs Vout, VNa, VK.

We will approach this project in a few steps.

Passive Channel Transistor Model

First, we want to measure a transistor (pFET) as a passive channel, as the prototype for a passive biolgical channel. We will use an FG OTA to input the current into the system; assume the maximum current of the tanh is in fact what is programmed for the device (will be slightly different, but nearly zero impact on your results).

You should have the source as the membrane voltage, the drain at GND, and you should bias the gate at a useful fixed potential for the circuit. The gate voltage will be directly related (and easy to model...hint for writeup) to the bias current you use for your OTA device. You might find it will help to program your OTA device, and sweep your pFET gate voltage to find a maximum response. You may, and are encouraged to do so, to have a pFET FG.

You will have capacitance from the line which serves fine as the membrane capacitance, From a small-signal step response, estimate the size of your capacitance.

You will want to think about the resulting dynamics in terms of membrane current. We have a dual representation between current and voltage through the pFET device.

In case you are looking for what a plot might look like, Vg at 0.1 V, EK at 1.35V, we have plots, sweeping from 0V to 2.5V where we are explicitly using an ammeter to measure the current. The first plot is for linear scale, and the second plot is log scale, taking the abs( ) of the mesaured current.

Channel Gating Transistor Models

Second, we want to build the basic channel gating models, and show their experimental results. We need to build a circuit for both the Na and the K gating channel dynamics. For our modified FPAA modeling, we will use a pFET transistor for the channel transistor for the Na (bandpass) channel, and we will use a nFET transistor for the channel transistor for the K (lowpass) channel, different (but equivalent) from the classical circuit approach. The primary reasons for modifications are utilizing the opportunities we have for implementing this entire structure with the FPAA resources, as well as implementing in a single CAB.

You will be making voltage-in to voltage-out responses from your membrane voltage to your Na or K gating potential. In each of these cases we are looking at step responses as well as frequency responses of the resulting devices. Make sure that you are careful when interpreting your results (which is always required) that you look at the resulting input and output amplitudes of the device.

Na Channel Gating Circuit : The circuit we will use looks similar to the device classically used. In this case, we will take the bandpass filter amplifier used for the Na Gating function and measure its resulting properties. You might realize that we are modifying the original element, because of its easier implementation on the FPAA device. You might also realize that our element is similar to the C4 filter structure, but with a transistor in the feedback loop. Your job is to show voltage input step responses that are similar to the classical form, including tuning for the resulting timeconstants (and gain, where useful. Typically we don't have a cap in feedback to stablize gain becaue the corners are already near enough to each other. Remember, that the membrane voltage would not grow more than 150mV.

K Channel Gating Circuit : Again, we are modifying the classical K Channel gating circuit for use in the FPAA device. The primary reason is the original circuit was a high-pass circuit, to match the dynamics, with a gain near 1 for higher frequencies; a lower gain will lead to troubing dynamics. In an FPAA, we have significant capacitance due to routing, so given our cap elements we have, it would be hard to get a gain much larger than 1. So, as a result, we want to take a different approach, one that was considered actually before this high pass structure, to make the system work:

Your goal is to again show by step responses that we get the classic voltage clamp type responses one expects for the gating voltage. One key item to remember is that in an FPAA, the effective space we need for a transistor or an OTA is roughly similar, particularly in terms of routing lines, so in this case, the metrics for area are different to optimize. In our case, getting the entire circuit in one CAB would be the ideal.

Building the transistor channel model for the HH squid axon preparation

Finally, we want to put together the classical HH model with a sodium and potasium channel device. Remember you have a working version of this circuit in the FPAA examples, so you should start from that place, which has good starting working parameters. Understand that tuning and getting data on this circuit working is worth a significant amount credit for this project, although if you don't do the first steps, you will have trouble with this last part.

Remember that the voltage difference between your ENA and EK needs to be around 140-150mV. Alot of our signal activity will happen near but just above EK.

The good part of this project is that the core circuit is already build for you, both a device with pins available (if buffered by OTAs) for this neuron block, and one without the pins available. The one with the pins is for setting the dc parameters and initial characterization; you will want final spiking data on the device without these aspects.

You will need to supply an input current for this system. The block achieves this goal using a non-FG OTA to do a somewhat linear voltage to current relationship. On the otherhand, you can also use any other device to input continuous time current for your choosing. If you want to use a routing floating-gate pFET element, that would also work nicely, and has some connection to synapse type blocks.

Expect you might have to change your parameters some from the previous cases as you put together your neuron.

First, show a classical spiking response for an input current step. You will want to use some different input current steps, which might require dividing down the input signal (the input goes into a non-FG OTA device).

Next, perform another experiment for an input current signal, such as having a ramp input between two current points, looking at the neuron response for a "constant" input just below the current threshold, etc.

Some additional thoughts on getting the FPAA working :