FPAA Tools, Infrastructure, and Class Papers
Applications Built / Compiled on FPAA Device Papers
SoC FPAA Devices
- Foundational Paper for the first SoC FPAA IC.
SoC FPAA pdf
S. George, S. Kim, S. Shah, J. Hasler, M. Collins, F. Adil, R. Wunderlich, S. Nease, and S. Ramakrishnan
"A Programmable and Configurable Mixed-Mode FPAA SOC,"
IEEE Transactions on VLSI, January 2016.
- Programming Infrastructure used in the SoC FPAA IC.
FG Programming pdf
S. Kim, J. Hasler, and S. George,
"Integrated Floating-Gate Program- ming Environment for System-Level ICs,"
Transactions on VLSI, January 2016.
- High Level Tools Paper pdf
M. Collins, J. Hasler, and S. George,
"An Open-Source Tool Set Enabling Analog-Digital-Software Co-Design,"
Journal of Low Power Electronics and Applications,
FPAAs IC Historical Approach
- First of the CADSP lab's fpaa papers,
and first approach discussing FG switches for routing.
T. Hall, D. Anderson, and P. Hasler,
"Field-programmable analog arrays: A
Field Programmable Logic and Applications,
Montpellier, France, September 2002.
12th Int. Conference Field Programmable Logic and Applications,
Montpellier, France, Sep. 2002, pp. 424-433.
- Journal Paper on the RASP 1.5 FPAA device.
The device showed experimental data from what would be the eventual 2.0 architecture
as a 2-CAB format.
The resulting approach showed both the routing density,
as well as potential FPAA size and scaling.
CAS I: pdf
T.S. Hall, C. M. Twigg, J. D. Gray, P. Hasler, and D. V. Anderson,
"Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing,"
IEEE Transactions on Circuits and Systems I, vol. 52, no. 11, Nov. 2005, pp. 2298.
T. S. Hall, C. M. Twigg, P. Hasler, and D. V. Anderson,
"Developing large-scale field-programmable analog arrays,"
Proc. 18th Int. Parallel and Distributed Processing Symp., Santa Fe, NM, Apr. 2004.
First discussion of Switches are not dead weight in our FPAA architectures.
Demonstration of a VMM, although not a typical characterization.
C. M. Twigg, J. D. Gray, and P. Hasler,
"Programmable floating gate FPAA switches are not dead weight,"
IEEE International Symposium on Circuits and Systems, May 2007, pp. 169 - 172.
- Paper on the RASP 2.5 GT IC, which was the starting prototype
for the next generation of FPAA devices.
C. M. Twigg and P. Hasler,
"A large-scale reconfigurable analog signal processor (RASP) IC,"
IEEE Custom Integrated Circuits Conference, Sept 2006, pp. p5-8.
- FPAA overview paper summarizing the state of ICs, infrastructure, and tools
through the RASP 2.7 ICs.
The paper gives a summary of FPAA devices through this particular time.
C. Twigg and P. Hasler
"Configurable analog signal processing,"
Digital Signal Processing vol. 19
Available online at www.sciencedirect.com since 3 October 2007.
First widely used FPAA IC (RASP 2.8)
A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan,
C. Petre, S. Koziol, F. Baskaya, C. M. Twigg, and P. Hasler
"A Floating-gate based Field Programmable Analog Array,"
IEEE Journal of Solid State Circuits,
vol. 45, no. 9, Sept. 2010. pp. 1781-1794.
A. Basu, C. Twigg, S. Brink, P. Hasler, C. Petre,
S. Ramakrishnan, S. Koziol, and C. Schlottmann,
"RASP 2.8: A new generation of floating-gate based field programmable analog array,"
IEEE Custom Integrated Circuits Conference, Sept. 2008, pp. 213 - 216.
Early FPAA specialized for Transistor Channel Models with examples (TBioCas)
A. Basu, S. Ramakrishnan, C. Petre, S. Koziol, S. Brink, and P. Hasler,
"Neural Dynamics in Reconfigurable Silicon,"
IEEE Transactions on Biomedical Circuits and Systems, vol. 4, no. 5, Oct 2010, 311-319.
Early FPAA specialized for sensor interfaces
S-Y Peng, G. Gurun, C. M. Twigg, M. S. Qureshi, A. Basu, S. Brink, P. Hasler, and F.L. Degertekin,
"A Large-Scale Reconfigurable Smart Sensory Chip,"
ISCAS 2009. May 2009, pp. 2145 - 2148.
FPAA modified for MITE circuits (TVLSI)
and P. Hasler,
"Programmable and Configurable MITE Systems enabled through Precise Floating-Gate Programming,"
IEEE Transactions on VLSI, Vol. 20, No. 1, January 2012.
FPAA employing fast dynamic reconfigurability
JSSC: pdf ,
CICC: pdf ,
"A Digitally Enhanced Dynamically Reconfigurable Analog Platform
for Low-Power Signal Processing,"
IEEE Journal of Solid State Circuits, vol. 47, no. 9, Sept 2012.
C. R. Schlottmann, S. Nease, S. Shapero, and P. Hasler,
"A Mixed-Mode FPAA SoC for Analog-Enhanced Signal Processing,"
FPAA integrating FPGA fabric into single architecture
R. Wunderlich, F. Adil, and P. Hasler,
"A Floating Gate Based Field Programmable Mixed-Signal Array,"
IEEE Transactions on VLSI, vol. 21, no. 8, 2013, pp. 1496-1505.
FPAA fabric enabling adaptive FG circuits.
S. Brink, J. Hasler, and R. Wunderlich,
"Adaptive Floating-Gate Circuit Enabled Large-Scale FPAA,"
IEEE Transactions on VLSI Systems, 2014.