Digital Design Laboratory
Summer 2025 (GT Metz)

Course Material Overview

The class is divided into two exam, a practical exam, eight projects, and a final design project.

Topic
Exam
Proj
On-Line Lectures
Week 1
(D: May 13
L: May 16 )
Class Intro Lab 0: Quartus
Draw Schematics
FPGA pin assign
Week 2
(D: May 20
L: May 19)
Combinatorial
Digital Logic
Waveform Gen
FPGA targeting
(May 25)
Two-Input NAND
Week 3
(D: May 27
L: May 26)
Digital Circuits
and K maps
Combinatoral
Circuit Prototyping
Pull up Resistors
(Jun 1)
Week 4
(D: June 3
L: June 2)
HDL Intro
Propagation Delays
Rise / Fall Times
HDL Intro
Wavefor Analysis
Oscilloscope
Worst-case delay
(Jun 8)
Legacy Circuit
Week 5
(D: June 10
L: June 13)
State Machine
Design
June 10
Su2025
Breadboard State Machine
Waveform Analysis
Worst-case delay
Quartus tools
(Jun 23)
Week 6
(D: June 17
L June 16)
VHDL State
machines
VHDL state machine
Logic Analyzer
(Jun 22)


Week 7
(D: June 24
L: June 22))
State Machines State Machines
VHDL Synthesis
Train Impl
(Jun 29)

Week 8
(D: July 1
L: June 30)
Intro. Simple
Computer (SCOMP)
CPU, memory, assembly
SCOMP
Tracing execution
(Jul 6)
Week 9
(D: July 8
L: July 7)
Assembly
Subroutines
Subroutines
SCOMP I/O
Small Game
(Jul 13)
Week 10
(D: July 15
L: July 18)
July 15 Lab Pract: July 18
Final Proj Intro

Week 11
(D: July 22)

Week 12

Key Link