- MOSFET as an approximate current source
- Basic MOSFET Circuits: Common-Source, Common-Gate, Source Follower, Differential Pairs
- Transconductance Amplifiers / Basics of FG Circuits

- Chapter 5 Material : OTA Circuit basics, Differential Transistor Pairs
- Chapter 6 Material : Cool Circuit Techniques
- Chapter 9 Material : Follower-Integrator Circuit
- Slide on subthreshold transfer functions
- Classic paper on Neural Amplifiers and Sub VT--Above VT Design
- Clasic paper on transistor noise

- Lecture One Transistor Circuit Basics
- Lecture Common Source and Gate Amplifiers
- Lecture Cascode Circuit Analysis
- Lecture Differential Pair Circuit Configuration
- Lecture Differential Voltage Amplifier
- Lecture Small Signal MOSFET Modeling
- Lecture Linear Analysis for First Order device
- Lecture First-Order Filter Dynamics
- Lecture Tuning OTA Amplifiers
- Lecture Nonlinear Amplifier dynamics

- Lecture 9 Boards: 1 , 2 , 3 ,
- Lecture 10 Boards: 1 , 2 , 3 , 4 , 5 , 6 ,
- Lecture 11 Boards: 1 , 2 , 3 , 4 ,
- Lecture 12 Boards: 1 , 2 , 3 , 4 , 5 , 6 ,
- Lecture 13 Boards: 1 , 2 , 3 , 4 , 5 ,
- Lecture 14 Boards: 1 , 2 , 3 , 4 , 5 ,
- Lecture 15 Boards: 1 , 2 , 3 , 4 ,
- Lecture 16 Boards: 1 , 2 , 3 , 4 ,
- Lecture 17 Boards: 1 , 2 , 3 , 4 , 5 ,

This project will leverage our measured results that we built our simulation model in the last project to look at MOSFET circuits, their IC design, and the resulting issues in circuit design. This project will look at MOSFET transistor circuits, in analysis, in simulation, and in IC layout. This project will focus on capacitors, particularly questions of MOSFET parasitics.

This project will consider

- source follower and common source amplifier.
- This project will investigate differential pairs and differential amplifiers.
- This project will require the design of amplifier using a transconductance topology. In particular, you will use a 9-transistor amplifier design and add the appropriate cascode devices.

Please remember "kappa" does not equal 1 anywhere in this project. You have transistor values from your previous project, and you should use them, assuming you had correct values. If you do not have confidence in your values, you have access to the other projects for correct values.

I do not need a detailed derivation in the presentation, just 1-2 highlights. Most derivations can be done effectively by inspection with the right intuition.

For the particular bias currents required, you might need to have biases or inputs
that are outside the power supplies (below GND or above Vdd).
This should only be effectively necessary for the
common-drain and common source amplifiers.
Other cases should happen as part of the circuit.
This occurs because of the low-current biases that you are trying to
achieve with the low V_{T0}.
Another way to achieve this case is taking your source terminal
up from GND (or down from V_{dd}),
which would happen in practical circuits.

For this project, you will want to use the following capacitances for your
capacitance modeling:
C_{ox} = 10.4fF/ um^{2},
C_{ol} = 0.1fF / um,
n+ diffusion (0 bias) area capacitance to substrate:
C_{j0n} = 0.8fF/ um^{2},
n+ diffusion (0 bias) perimeter capacitance to substrate:
C_{jswn} = 0.034fF / um,
p+ diffusion (0 bias) area capacitance to substrate:
C_{j0p} = 1.05fF/ um^{2},
p+ diffusion (0 bias) perimeter capacitance to substrate:
C_{jswn} = 0.047fF / um,

- Transistors for this part require W/L = 800nm / 400nm (Drawn values).
- You should have a load capacitance of 100fF. In your simulation, just use a single capacitor of this size.
- Set gate voltage for the bias transistor such that the bias current would be 100pA. Identify that particular voltage.

** Source-Follower Circuits **

** Analysis **:
For your source-follower circuit:

- What is the voltage gain from input to output? How does the gain change from subthreshold to above-threshold bias currents? Where is the gain region of the circuit?
- From your data and analysis of the source follower, you can find kappa as a function of source voltage. It turns out this configuration is a good measurement of how kappa changes for a fixed bias current. Compute a numerical derivative of the data and discuss your results. Discuss how this change in "kappa" would be related to changes in depletion capacitance.
- What is the corner frequency of this circuit for the bias current listed above? What is the linear range of this circuit?
- What is the total noise (output) of this circuit? How does total noise (output) of this circuit change with subthreshold bias currents? Qualitatively, how does it change for above threshold bias currents?

- Simulate a transfer curve for your Source-Follower circuit. Identify the operating regime for the amplifier circuit, that is, the place where both transistor are operating in saturation. Identify the slope of the amplifier in this region, and compare the value to your analytic results.
- Simulate the amplifier with a upgoing and downgoing step response (a square wave). Use two step amplitudes, one smaller than the amplifier's linear range and one larger than the amplifier's linear range. Curve fit for the time constant and the linear range of the amplifier for both signals. Which parasitics made the biggest difference between your theory and simulation?
- In practice, the source follower will not have constant gain because of kappa shift. Does the simulation show this change? What do you get for kappa versus output voltage? Need numerical derivative.
- What is the total measured output noise (thermal) of this circuit?

** Common-Source Circuits **

** Analysis **:
For your common-source circuit:

- What is the voltage gain from input to output? Where is the gain region of the circuit?
- How does this gain depend upon bias current in subthreshold? Quantitatively explain how the gain changes for above threshold current levels.
- If you needed a very high gain amplifier of this type, how would your design your transistors to achieve this very large gain?
- What is the corner frequency of this circuit for the bias current listed above? What is the linear range of this circuit?
- What is the total noise (output) of this circuit? How does total noise (output) of this circuit change with subthreshold bias currents? Qualitatively, how does it change for above threshold bias currents?

- Simulate a transfer curve for your Common-Source circuit. You will likely want a sweep over the operating range to find the gain region. Then, obtain a dense sweep of the transfer curve between the amplifier (gate) input and the amplifier output (drain). Notice where the data makes a sharp transition, and relate this value to measured parameters and bias voltages. Find the gain, and compare to your values of Early Voltage (sigma), kappa, and UT.
- Make a single plot of the output voltage versus the input voltage for this amplifier. Curve fit the gain of the amplifier Identify the operating regime for the amplifier circuit, that is, the place where both transistor are operating in saturation. Identify the slope of the amplifier in this region, and compare the value to your analytic results.
- Simulate the amplifier with a upgoing and downgoing step response (a square wave). Use a step amplitude such that both transistors are in saturation for the entire response, that is, you are in the high-gain region of the amplifier. Curve fit for the time constant of the amplifier. Which parasitics made the biggest difference between your theory and simulation?
- What is the total measured output noise (thermal) of this circuit?

- Transistors for this part require W/L = 800nm / 400nm (Drawn values).
- You should have a load capacitance of 250fF. In your simulation, just use a single capacitor of this size.
- Set gate voltage for the bias transistor such that the bias current would be 1nA. Identify that particular voltage. This would be a subthreshold bias current.

** Differential Pairs **:
Start by creating your layout of your differential pair with an nFET current source
bias transistor.
Consider the following questions:

- Assume that the biasing current source transistor for a differential pair is operating with subthreshold currents. Explain if one can assume the differential pair devices are in subthreshold?
- What is the minimum drain-to-source voltage required for this biasing current source transistor if it is operating with subthreshold currents?
- Derive the differential-pair output currents as a function of the two differenital input voltages and the bias current, assuming all transistors operate sub threshold. You should neglect the effect of Early voltage (channel length) for this calculation.
- If V1 << V2, simplify the above expressions for I1 and I2. You will find this expression helpful for some of the experimental curve fits.
- Simulate for currents versus differential input voltage. Currents versus common-mode input voltage. How much does it change? How does it relate to sigma / Early effect?

** Differential Amplifiers **:
Start by creating your layout of your 9 Transistor amplifier.
Use the differential pair you built above.
Continue to use the same 1nA bias current.
Consider the following questions:

- Simulate the transfer curve response for your amplifier keeping the negative
input terminal fixed between the power supply rails (say half of V
_{dd}). What you need to do is do a voltage sweep on the inputs, keeping one input fixed, and measure the output response. You might need to do a course sweep and then a fine sweep to get the gain region. Identify key regions of the graph. - Connect your amplifier as a unity-gain amplifier. We call a follower--integrator circuit (follower for low frequency operation). Perform a transfer curve for this amplifier (a sweep of the output voltage versus input voltage ). Does anything unexpected happen as the input voltage approaches GND? Make a plot (linear scale) of Vout vs. Vin, with a curve fit over the linear region. Is the gain exactly equal to 1? Discuss how this result is a function of differential mode and common-mode gain.
- Input a square wave input (like the above experiments) where one input is smaller than the input linear range, and one input is larger than the input linear range. Analytically calculate your expected timeconstants. What do you expect your linear range would be? Extract the timeconstant and linear range from these step responses. Determine the time constant of the integrator by curve fitting for your timeconstant (removing steady state, looking at log of the remaining abs of the response). What is the load capacitance? Is there any difference between the rise and fall times? Curve fit response to linear response (exp( -t / tau) ) to determine the time constant of the integrator in both cases, as well as the linear range, where applicable. What parasitics changed your values from your theoretically expected results?

** Transconductance, Output Resistance, and Gain**:
This part will quantitatively show the relationship between transconductance,
output resistance, and voltage gain for your amplifier circuit.
Again, you will use a 1nA bias current,
and will use the amplifier in its open-loop configuration.

- Explain how you would measure the voltage gain for a transconductance amplifier if you were given an ammeter and variable voltage source. How will you compute the output resistance, Rout, and transconductance, Gm, from experimental measurementsr?
- From your previous simulations, calculate what the transconductance would be for this amplifier in its linear region. Transconductance is asking what is the change in output current for a change in input voltage.
- From your transfer function, calculate the gain of this amplifier in its gain region (all transistors in saturation).
- Perform a large-signal sweep of output current versus input current. Note where transistors are in saturation and when not in saturation. In the linear region for the graph, calculate the resulting output resistance.
- compare your three results. Do they agree, and how close do they agree?

Using a transconductance amplifier topology, your group is required to design the device to typical on-chip operational amplifier specifications. Each group will have different specfications.

The design must have layout, LVS, and extraction. You have one amplifier design that you will perform the resulting post-layout simulation tasks. You have full control over the W/L of all devices. Most W/L won't have a major effect on your design.

Area must be minimized, and will be assessed as part of your grade.

The gain of your amplifier is required to be 10,000. You would expect to need cascade devices at the output node.

Capacitive load = 250fF. You can add more as required.

You will be responsible for the basing circuitry.
You can assume the V_{tau} will be provided to you through biasing circuitry.
You need to determine what that value will be. Otherwise,
You need to generate any required cascade voltages using transistor elements.

Your group must comment on the impact of
transistor mismatch (e.g. cascade voltage, input offset).
Two nearby 1200nm/1200nm transistors will have roughly 10mV V_{T0} mismatch.
Your analysis requires having a discussion of transistor mismatch effects on your circuits.

Assume the input range for this amplifier must be valid
(specifications must hold) for voltages between 0 and 1V.
The output voltages need to be valid between 0.3V and 1.2V.
V_{dd} = 1.5V for this design.

Total thermal output noise is 1mV rms when the amplifier is connected in its unity-gain configuration. The value would be equivalent to its total input referred noise. Discus the noise per root Hz, and the resulting relationship required.

Your power consumption is limited to 3 times your
differential amplifier bias current from V_{dd} to GND.

Unity-Gain frequency will be given to each group. You should measure the slew rate of your amplifier, and relate it to your bias current, as well as relate it to your unity-gain frequency.

Need to have 45 degree phase margin. You might need to add capacitance at the output to guarrentee this result. Or you might be able to shift your transistor sizes to minimize some capacitances.

Bias current needs to be minimized. I am expecting the bias current required for the ideal subthreshold response into the original capacitive load. I expect you will be able to justify this value for your given frequency response.