Basic Transistor Circuits

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This project will leverage our measured results that we built our simulation model in the last project to look at MOSFET circuits, their IC design, and the resulting issues in circuit design. This project will look at MOSFET transistor circuits, in analysis, in simulation, and in IC layout. This project will focus on capacitors, particularly questions of MOSFET parasitics.

This project will consider

Please remember "kappa" does not equal 1 anywhere in this project. You have transistor values from your previous project, and you should use them, assuming you had correct values. If you do not have confidence in your values, you have access to the other projects for correct values.

I do not need a detailed derivation in the presentation, just 1-2 highlights. Most derivations can be done effectively by inspection with the right intuition.

For the particular bias currents required, you might need to have biases or inputs that are outside the power supplies (below GND or above Vdd). This should only be effectively necessary for the common-drain and common source amplifiers. Other cases should happen as part of the circuit. This occurs because of the low-current biases that you are trying to achieve with the low VT0. Another way to achieve this case is taking your source terminal up from GND (or down from Vdd), which would happen in practical circuits.

For this project, you will want to use the following capacitances for your capacitance modeling: Cox = 10.4fF/ um2, Col = 0.1fF / um, n+ diffusion (0 bias) area capacitance to substrate: Cj0n = 0.8fF/ um2, n+ diffusion (0 bias) perimeter capacitance to substrate: Cjswn = 0.034fF / um, p+ diffusion (0 bias) area capacitance to substrate: Cj0p = 1.05fF/ um2, p+ diffusion (0 bias) perimeter capacitance to substrate: Cjswn = 0.047fF / um,

Two-Transistor Amplifiers

For each of these circuits,

Source-Follower Circuits

You need to make a source-follower circuit where the input signal goes into a pFET gate. You need to layout the source-follower circuit, include a picture of the layout (that agrees through LVS), and use your layout to extract for your simulation file.

Analysis : For your source-follower circuit:

Simulation : For your source-follower circuit:

Common-Source Circuits

You need to make a common-source circuit where the input signal goes into an nFET gate. You need to layout the common-source amplifer, include a picture of the layout (that agrees through LVS), and use your layout to extract for your simulation file.

Analysis : For your common-source circuit:

Simulation : For your common-source circuit:

Differential Pairs and Amplifiers

For each of these circuits,

Differential Pairs : Start by creating your layout of your differential pair with an nFET current source bias transistor. Consider the following questions:

Differential Amplifiers : Start by creating your layout of your 9 Transistor amplifier. Use the differential pair you built above. Continue to use the same 1nA bias current. Consider the following questions:

Transconductance, Output Resistance, and Gain: This part will quantitatively show the relationship between transconductance, output resistance, and voltage gain for your amplifier circuit. Again, you will use a 1nA bias current, and will use the amplifier in its open-loop configuration.

Amplifier Design project

Using a transconductance amplifier topology, your group is required to design the device to typical on-chip operational amplifier specifications. Each group will have different specfications.

The design must have layout, LVS, and extraction. You have one amplifier design that you will perform the resulting post-layout simulation tasks. You have full control over the W/L of all devices. Most W/L won't have a major effect on your design.

Area must be minimized, and will be assessed as part of your grade.

The gain of your amplifier is required to be 10,000. You would expect to need cascade devices at the output node.

Capacitive load = 250fF. You can add more as required.

You will be responsible for the basing circuitry. You can assume the Vtau will be provided to you through biasing circuitry. You need to determine what that value will be. Otherwise, You need to generate any required cascade voltages using transistor elements.

Your group must comment on the impact of transistor mismatch (e.g. cascade voltage, input offset). Two nearby 1200nm/1200nm transistors will have roughly 10mV VT0 mismatch. Your analysis requires having a discussion of transistor mismatch effects on your circuits.

Assume the input range for this amplifier must be valid (specifications must hold) for voltages between 0 and 1V. The output voltages need to be valid between 0.3V and 1.2V. Vdd = 1.5V for this design.

Total thermal output noise is 1mV rms when the amplifier is connected in its unity-gain configuration. The value would be equivalent to its total input referred noise. Discus the noise per root Hz, and the resulting relationship required.

Your power consumption is limited to 3 times your differential amplifier bias current from Vdd to GND.

Unity-Gain frequency will be given to each group. You should measure the slew rate of your amplifier, and relate it to your bias current, as well as relate it to your unity-gain frequency.

Need to have 45 degree phase margin. You might need to add capacitance at the output to guarrentee this result. Or you might be able to shift your transistor sizes to minimize some capacitances.

Bias current needs to be minimized. I am expecting the bias current required for the ideal subthreshold response into the original capacitive load. I expect you will be able to justify this value for your given frequency response.