Preprocessing verilog.
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Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)
Email: jamieson.peter@gmail.com and ken@unb.ca for support issues

Reading Configuration file
Reading FPGA Architecture file
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High-level synthesis Begin
Parser starting - we'll create an abstract syntax tree.  Note this tree can be viewed using GraphViz (see documentation)
Optimizing module by AST based optimizations
Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)

Hard Logical Memory Distribution
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SPRAM: 2 width 18 depth

Total Logical Memory Blocks = 1 
Total Logical Memory bits = 524288 
Max Memory Width = 2 
Max Memory Depth = 18 

Performing Optimizations of the Netlist
Performing Partial Map to target device
Check for liveness and combinational loops
Outputting the netlist to the specified output format
Successful High-level synthesis by Odin
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Hard Multiplier Distribution
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Total # of multipliers = 0
