An Interesting Op-Amp Characterization Problem

You have another friend making op-amp Integrated Circuits (IC) who is not from GT. In this case, your friend designed a very fast op-amp circuit that was fabricated in a good CMOS IC process. They have questions that require an expert opinion, and so they contacted you.

Your friend made a chip with two amplifiers (and some other items). For these two amplifiers (Fig. 1), CMOS switches were included on chip for each of the two amplifiers to be a typical op-amp circuit or have an internal direct connection between the -terminal and the output (unity-gain configuration). Unfortunately, there was an error in the digital logic selecting these options, and one amplifier is always in the typical op-amp configuration, and the other amplifier is always in the unity-gain configuration. IC design is hard, and often one finds an error after the chip is fabricated. Both op-amps were designed to be identical.


Figure 1: Designed and actual two amplifier configurations. The fabricated chip is the actual two amplifier configurations.

The op-amp was designed for a low-frequency gain of 3000 with a corner frequency of 3.3MHz. The resulting unity gain frequency is roughly 10GHz. Experimental measurements show roughly a similar

This friend made sure to do a unity-gain simulation for their design, and achieved 45degrees phase margin at the unity gain frequency (10 GHz, 10pF load). The amplifer can be well described by two poles.

For those who understand IC design, the first stage is an OTA topology with cascode outputs, and the second stage is approximately a unity-gain buffer circuit.

The circuit is capable of driving upto a 10pF external load, and all experiments satisfy that requirement. The two amplifiers separately were experimentally verified on a PCB built for these measurements.

So everything should be in good shape, except that your friend tried one more experiement that created alot of confusion. The individual decided to take the first case of the actual circuits (V1+ and V2+ ) and put an additional wire trace on one of the working PCB to make a unity-gain configuration. The results were best described by your friend as "weird". You might be thinking that means unstable, and that is makes sense, but how and why?

You ask your friend two questions:

  • what is the estimated capacitance of the line?
  • what the length of the line?
Your friend gives you that information, including that the capacitance of the line is roughly 7pF. When you got the length of the line, you realize at the expected unity gain frequency you would have 8 wavelengths through the wire. Although one assumes a line is simply potential capacitance, it is more accurately modeled with an inductor (L) and capacitor (C) network (Fig. 2). It seems should approximate the wire as seven to eight taps of an LC line. You would want to model this case at C = 1pF and L = 10nH (Fig. 2).


Figure 2: A drawn wire not only has capacitance, that capacitance is a distributed capacitance and inductance between each stage. Multiple inductor (L) -- capacitor (C) elements typically are used to approximate the continuous delay line.

Your friend is concerned, as one does not know what to believe. Your friend believes the best way to validate his design is to make a control system around it that would stabilize the one amplifier with the wire between the two terminals. Controlling this system models what is happening in the original system, and therefore, validate the original design.

Your task : Analyze the original system, build an optimal controller for this system, and use this analysis to interpret the behavior of this amplifier system.

You have one input and one output for this system with the wire connecting between the -terminal and the output terminal. Measurement at the - terminal might further affect the dynamics, and we want to avoid that issue.

For the system, you should assume an total input referred noise level of 30uV. You should also assume there is variation in the particular values in the wire by 10 percent.

You would want to consider whether the system is stable, what the eigenvalues and eigenvectors would be, whether the system is controllable and observable, what are the components for LGQ, and what is the resulting transfer function.

You need to show the freqwuency responses for the uncontrolled system (open-loop), original controlled system (closed-loop), and new controlled system (closed-loop) given your controlller. You should not use "dB" units at all; you should have plots in "loglog" or "semilogyx" or "semilog y" style, and your measurements should be realistic and have physical meaning. You would expect the phase near 0Hz to be 0 (or 0 degrees) for all of these systems.