Analog System Design Project

The focus on this fourth design project is to develop a design of an analog system.

Materials on IC system design

Notes on basic Filter architecture .
Notes on fundamentals of capacitor circuits as well as basic switched capacitor circuits .
Notes on basic sample and hold circuits . Further, we include the classic two papers on charge feedthrough modeling pdf , and pdf .
Notes on starting point for comparitor circuits .
Notes on basics of Data Converter circuits , on Digital to Analog Converters (DAC) circuits , and on High Speed Analog to Digital Converters (ADC) circuits .
Classic capacitor sensor front-end by S. Y. Peng , et. al.
Bandpass Filter Paper C⁴
Winner-Take-All Circuit paper
Classic paper on matching in semiconductor devices

Outside Resources that might be useful

Overview slides from TAMU on Sample and Hold blocks
Overview notes on Continuous-time Filter approaches at UC Berkeley blocks
Overview notes by G. Temes (OSU) on Continuous-Time Active Filters blocks
Overview notes on Switched Capacitor Filter approaches at UC Berkeley blocks
Overview notes on Switched Capacitor approaches at U of Calgary blocks
Overview talk by David Narim when he was working at ADI, pdf , and gave this presentation at GT at that time.

Lecture Boards

Lecture on ADC Architectures and some approaches: 1 , 2 , 3 , 4 ,
Lecture on Current DACs / Successive Approx ADCs: 1 , 2 , 3 , 4 , 5 , 6 , 7 ,
Lecture on Charge DACs / Switch Cap 01: 1 , 2 , 3 , 4 , 5 ,
Lecture on S/H circuits / What can go Wrong with Switch Cap: 1 , 2 , 3 , 4 , 5 , 6 ,

Analog System Design Description

In this project, we are going to be building a key component of a typical analog system chain. Classical design architectures process from the input analog sensor through its arrival as a clocked digital signal. A typical analog system block for sensor inputs would include a temperature sensors, a microphone sensor, ultrasound sensor, sensing data from a hard drive, or even sensing wireless signals.

Each team will be building a core block of a resulting system. We can discuss in class how these blocks would work together. These blocks will be built into a configurable infrastructure, providing the infrastructure required for directly using Floating-Gate (FG) transistors. Anotherwords, there will be standard programming infrastructure available; your cells need to have the necessary connections if you use this approach.

For all designs, optimizing power consumed as well as area are critical for both designs. The power supply for the IC will be 1.5V, and will use the same process we hve all semester. The layout and post-layout simulation for this project is essential.

As this design is a physical design, you should be aware of design mismatch on your IC, where appropriate. Dealilng with mismatch is a critical graded component. You should discuss the effect of temperature on your design, if it is present at all. You effectively do not have any explicit inductors or resistors, other than a single resistor for setting current in a bootstrap reference.

Application1: Front-end System design for Neural Recording

Figure 1: Basic Two device beamforming architecture for two sensors in an endfire configuration.

The goal of this project is to build the accoutic front-end signal processing for a two-input beamforming system as part of a wireless headset. Beamforming is used to improve the SNR of the transmitted signal. The beamforming described here reduces the background noise by placing a null in a non-preferred direction. Figure 1 shows the architecture for this system. The output quality needs to be good enough to be used for Voice over IP quality, Your inputs start from Analog capacitive-sensing LNA modules, originally developed by S.Y. Peng, et. al (in our circuit references).

Area must be minimized because the circuit will fit ideally in an area containing the two microphones and the resulting circuit. Power must be minimized because it will be in a power constrained environment (a wireless headset) where one does not want to charge the battery often.

This project will have two parts. One group (team 1) will build the beamforming front-end circuitry and one group (team 2) will build the output Analog-to-Digital Converter.

Beamforming Front-End Circuitry

This circuitry will primarily be selecting Assume the input LNAs give 12bit SNR outputs or higher for your consideration. You will want to be able to select between at least two null positions. Your output signal must be

Bandwidth = 8kHz, minimum required frequency is 40Hz.
SNR = 12bits (agregating stages versus cancelation effects)
Output Voltage Range = 1.0V

ADC Design

You will need to build an ADC to convert the output waveform to a digital form that could be transmitted by a standard zigbee module. The output signal will be a serial bit stream of the resulting bits, ideally an SPI bit stream. You will need an appropriate S/H stage before your ADC.

Sample Rate = 20kSPS
Linearity and Resoluton = 12bits (INL, DNL, spectrum test at 8kHz).
Input Voltage Range (Full Scale Range) = 1.0V, and must match the range of Team 1.

Application 2: Ultrasound In-vivo Imaging Receiver

The goal of this project is to build a front-end analog signal processing for a single channel of an ultrasound receiver used for in body (In-vivo) imaging. For the particular distances to measure, the ultrasound carrier frequency of the simulation and measurement is 30MHz. The resulting output bandwidth will be 1MHz.

Area needs to be minimized because of constraints for an implanted device, potentially in small areas like blood vessels. Power must be minimized since getting power into the body can be a challange (battery or wireless) and the implant should not affect the surrounding temperature.

This project will have two parts. One group (team 3) will build the analog front-end electronics, and one group (team 4) will build the Analog-to-Digital Converter.

Front-end design

This design will take the initial 30MHz front-end signal and create a bandlimited 1.5MHz signal.

You will need to downmix the 1MHz signal from its 30MHz carrier frequency.
The input signal has a maximum realistic size of 20mV.
You will want to have a mixer circuit to handle the resulting signal.
You will have to address how you will generate your 30MHz carrier frequency on-chip.
Your output signal must be bandlimited to 1.5MHz for the next stage to the level required for the 8bit ADC. Therefore, you need an appropriate filter for the 1MHz bandwidth signal.
Your output signal needs to be 1V output range with an 8bit SNR.

ADC Design

You need to design an appropriate Sample and Hold for the input of the ADC. You need to design the parallel output voltage register that will have the resulting ADC signal. You will need an appropriate S/H stage before your ADC.

Sample Rate = 3MSPS
Linearity and Resolution = 8bits (INL, DNL, spectrum test at 1MHz)
Input voltage range (Full Scale Range) = 1V and must match the range of Team 3.