System on Chip (SoC) large-scale Field-Programmable Analog Array

Lead Professor: Dr. Jennifer Hasler

SoC FPAA: Programmable and configurable, analog and digital, circuits, signal processing, algorithms, and systems. This focus is involved in signal processing, analog and digital integrated circuits and systems design, nonlinear dynamics, and CMOS device physics.

  • large-scale Field Programmable Analog Arrays (FPAA). First System on Chip (SoC) FPAA Integrated Circuit [1]
  • FPAA design tools [2].
  • SoC FPAA Classification and Learning. SoC FPAA paper had an initial acoustic classification algorithm.
    • Speech versus non-Speech Detection using VMM+WTA classifier ( pdf ) [4].
    • SoC FPAA on-chip VMM+WTA classifier Learning Algorithm: ( pdf )[5].
    • Implementation of On-chip SoC FPAA Machine Learning: ( Journal ) [6] ( GOMAC [7], and Conference [8].
  • FPAA classifier applications towards biomedical applications.
    Accoustic classification for Knee Diagnostics: pdf [9], and pdf [10].
    Hemodynamic Feature Extraction (pdf)[11].
  • FPAA board design / Educational Applications.
  • Floating-gate programming. SoC FPAA programming infrastructure [18].
  • Scaling of Floating-Gate Devices (350nm to 40nm) and Resulting FPAA architecture scaling [19]. and Initial 40nm FPAA design based on these approaches [20].
  • Built-In Self Test ( pdf ) initial paper [21].
  • Initial FPAA calibration paper: Conf [22], and Journal [23].
  • Design for Temperature empowered through FPAA SoC Devices. Techniques for low temperaturer-sensitive design, as well as fundamental subthreshold temperature modeling and design.
    FPAA design techniques ( pdf [24]) as well as temperature modeling and design ( pdf [25]).
  • Security for FPAA devices [26].
  • FPAA for solution of PDEs (pdf)[27].
  • Press articles on the SoC FPAA and infrastructure from Electronic Products [28] and GT press [29].
References :
[1] S. George, S. Kim, S. Shah, et. al, "A Programmable and Configurable Mixed-Mode FPAA SOC,” IEEE Transactions on VLSI, vol. 24, no. 6, 2016. pp. 2253-2261.
[2] M. Collins, J. Hasler, and S. George, "An Open-Source Toolset Enabling Analog–Digital–Software Codesign," Journal of Low Power Electronics Applications, January 2016.
[3] A. Natarajan and J. Hasler, ``Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA,'' Analog Integrated Circiuits and Signal Processing, vol. 91, no. 1, January 2017, pp. 119-130.
[4] S. Shah and J. Hasler, "Low Power Speech Detector On A FPAA," IEEE ISCAS , May 2017.
[5] J. Hasler and S. Shah, "SoC FPAA Hardware Implementation of a VMM+WTA Embedded Learning Classifier," IEEE Trans. ECAS , March 2018.
[6] S. Shah and J. Hasler, "VMM + WTA Embedded Classifiers Learning Algorithm implementable on SoC FPAA devices," IEEE Trans. ECAS , March 2018.
[7] J. Hasler and S. Shah, "Learning for VMM + WTA Embedded Classifiers," GOMAC, 2016.
[8] J. Hasler and S. Shah, "Enabling Embedded Learning and Classification Implemented on SoC FPAA Devices,"
[9] S. Shah, H. Treyin, O. T. Inan, and J. Hasler, “Reconfigurable analog classifier for knee-joint rehabilitation,” IEEE EMBC , August 2016.
[10] S. Shah, C. N. Teague, O. T. Inan, and J. Hasler, “A proof-of-concept classifier for acoustic signals from the knee joint on an FPAA,” IEEE SENSORS, October 2016.
[11] H. Toreyin, S. Shah, S. Hersek, Omer T. Inan, J. Hasler, "Proof-of-Concept Energy-Efficient and Real-Time Hemodynamic Feature Extraction from Bioimpedance Signals using a Mixed-Signal Field Programmable Analog Array," IEEE BHI 2017 , 2017.
[12] J. Hasler, S. Kim, S. Shah, F. Adil, M. Collins, S. Koziol, and S. Nease, "Transforming Mixed-Signal Circuits Class through SoC FPAA IC, PCB, and Toolset," European Workshop on Microelectronics Education, Southampton, May 2016.
[13] M. Collins, J. Hasler, and S. Shah, "An approach to using RASP tools in analog systems education," FIE , October 2016.
[14] J. Hasler, A. Natarajan, S. Shah, and S. Kim, "SoC FPAA Immersed Junior Level Circuits Course," MSE , May 2017.
[15] J. Hasler, "Circuit Implementations Teaching a Junior Level Circuits Course Utilizing the SoC FPAA,"
[16] J. Hasler, S. Shah, S. Kim, I. Lal, and M. Collins, "Remote FPAA System Setup Enabling Wide Accessibility of Configurable devices," Journal of Low Power Electronics Applications, June 2016.
[17] J. Hasler, S. Shah, S. Kim, I. K. Lal, and M. Collins, "Remote System Setup Using Large-Scale Field Programmable Analog Arrays (FPAA) to Enabling Wide Accessibility of Configurable Devices," Journal of Low Power Electroncs Applications, vol. 6, no. 14, 2016, pp. 1-17.
[18] S. Kim, J. Hasler, and S. George, "Integrated Floating-Gate Programming Environment for System-Level Ics," IEEE Transactions on VLSI , 2016.
[19] J. Hasler, S. Kim, and F. Adil, "Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems," Journal of Low Power Electroncs Applications, vol. 6, no. 13, 2016, pp. 1-19.
[20] J. Hasler andi H. Wang, “A Fine-Grain FPAA fabric for RF+Baseband,” GOMAC, 2015.
[20] S. Shah and J. Hasler, "Tuning of Multiple Parameters With a BIST System," IEEE CAS I, vol. 64, no. 7, July 2017, pp. 1772-1780.
[21] S. Kim, S. Shah, J. Hasler, "Floating-Gate FPAA Calibration for Automated Analog Circuit and System Design," IEEE ISCAS , May 2017.
[22] S. Kim, S. Shah, and J. Hasler, "Calibration of Floating-Gate SoC FPAA System," IEEE Transactions on VLSI , 2017.
[23] S. Shah, H. Toreyin, J. Hasler, A. Natarajan ``Temperature Sensitivity and Compensation On A Reconfigurable Platform,'' IEEE Transactions on VLSI , Vol. 26, no. 3, March 2018. pp. 604-607.
[24] S. Shah, H. Toreyin, J. Hasler, and A. Natarajan, ``Models and Techniques For Temperature Robust Systems On A Reconfigurable Platform,'' Journal of Low Power Electronics Applications, vol. 7, no. 21, August 2017. pp. 1-14.
[26] J. Hasler, "Security Implications for Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems,"
[27] J. Hasler and S. Shah, "Reconfigurable Analog PDE computation for Baseband and RF Computation," GOMAC , March 2017.
[28] Electronic Product Magazine, March 21, 2016. "New analog chip uses 1,000 times less electrical power (and can be built a hundred times smaller) than comparable digital devices"
[29] http://www.rh.gatech.edu/news/508791/configurable-analog-chip-computes-1000-times-less-power-digital