Project 3: Stability, Programmability, and further Amplifier Design
The goal of this project
is to understand stability in amplifier design,
as well as its implications for realistic analog design (e.g. parastic capacitors).
Further, this project explicitly allows using Floating-Gate (FG) circuit techniques
in the designs,
although not required for the design project.
You might find having these techniques helpful for your specifications.
- Chapter 9 Material : Follower-Integrator Circuit
- Chapter 10 Material : Attempts at Differentiators,
including a typically used second-order section called Diff2
- Chapter 12 Material : Second-Order Low-Pass Filter Stages.
- Tobi Delbruck's classic paper on the Adaptive Photoreceptor.
Your first design is related to this circuit.
This paper shows one particular application (of many) for this approach.
- Classic Floating-Gate
Circuit Approach for a Folded-Cascode Topology.
- Fundamental Paper on Noise in Transistors
Dr. Sarpeskhar (currently at MIT)
- Classic Design for an OTA-based, Low-Noise
- Classic C4 Paper (Bandpass SOS)
- Paper using FG devices for OTA based
- Lecture 18:
- Lecture 20:
- Lecture 21:
- Lecture 22:
- Lecture 23:
- Lecture 24:
- Lecture 25:
- Lecture 26:
You will have two designs to consider for this project.
Both designs require analysis, simulation, and IC layout.
You will use the same
You will use your previous IC process as well as simulation parameters for this design.
- A four-transistor trans-impedance amplifier (current in to voltage out) with voltage gain.
- A folded cascode CMOS on-chip op-amp.
The output stage will require cascodes on nFET and pFET devices, but just one cascode
(not a stack of two or more).
The particular circuit will be a small modification from the example design shown in class.
As an on-chip amplifier, you do not need to have low output impedance,
because the device is typically driving capacitive loads.
You will assume your device is driving a 0.3pF load.
You are allowed to add more capacitance if helpful.
In both cases, you must
You must show the step response for your designs.
Stability is defined as Q <= 1, which is equivalent to at least 45 degrees of phase margin.
For the amplifier design, this stability should be demonstrated
for the amplifier connected as a unity gain amplifier.
For both designs,
Area must be calculated and minimized.
These analytic questions will be quite helpful for you to understand your
Transimpedance Amplifier design.
You are Strongly encouraged to work through these questions before
starting your design.
The Questions will directly connect to Figure 1.
For the analytic questions, assume the ratio
between C1 and C2 is 10.
Assume typical device parameters ("kappa", "sigma") throughout the analysis.
You will be looking at large-signal and small-signal analysis approaches
through these questions.
Figure 1: Two candidate transimpedance circuits to convert an input current
to an output voltage.
(a) Basic transimpedance circuit.
(b) Frequency dependant transimpedance circuit.
High-frequency gain is higher than low-frequency gain.
Figure 1a shows a simple transimpedance amplifier using a single transistor.
This transimpedance amplifier has a log( i ) versus Vout.
Logarithmic receptors have a property that makes them good for sensory perception.
What is that property?
Sketch a plot of the expected output voltage as a function of the input current
over a couple orders of magnitude
with constant bias voltage.
What is the slope of the response?
Compute the large signal input-current--output-voltage relationship
of the two transimpedance amplifiers in Fig. 1a and Fig. 1b.
For Fig. 1b,
compute both the transient function and the DC function.
The transient function is the circuit response to a sudden change in the input current
(e.g. step function).
The DC function is the circuit response to a long steady input current.
Then make the assumption that
the gain of the feedback amplifier (the high-gain stage)
is large compared with the capacitive divider ratio.
What is the expected
gain of the common-source amplifier in Fig. 1b for subthreshold currents?
This computation shows that we can
safely make the assumption that amplifier gain is larger than the
attenuation from the capacitive divider.
Assume that the gain is not infinite, and
the response of the input node in response to i.
Consider Fig. 1a transimpedance amplifier considering small-signal inputs,
so we can use small-signal modeling for these expressions.
The small-signal cases will tell us about the speed of the circuit
in the case of a small perturbation on top of a large background signal,
which is the real-world situation.
From your above expressions, compute
the small-signal gain.
Small-signal gain is the output voltage change relative
to a small change i in input.
How do the logarithmic properties of the circuit in Fig. 1a appear in the
small-signal gain expressions?
What does ``small-signal'' mean in terms of the input intensity?
For Fig. 1a, the capacitance (Csensor)
and the background sensor current (Isensor) determine
how fast the receptor responds to a small change i in the intensity.
Compute the first-order time-constant of the response.
The following questions relate to time response for Fig. 1b,
and you can assume small-signal input signals.
Neglect the effect of the adaptive feedback element,
and the charge on the resulting "floating node" is fixed.
Compute the small-signal gain of the circuit.
What is the time-constant of the small-signal response
(assuming the feedback amplifier is much faster tthan sensor state variable)?
What is the total loop gain, of the circuit?
The total loop gain is the gain all the way around the loop,
multiplying all gain elements in series.
What is the speedup of Fig. 1b over the speed of the
Express this speedup in terms of the total loop gain.
Floating-Gate Circuit Design
This section is to start getting you use to working with Floating-Gate (FG) circuit techniques.
These techniques allow the user to program an analog value into a circuit.
Biasing techniques become straightforward if the required FG infrastructure if available.
In the next project, we will talk about how to integrate these devices into a programming infrastructure.
- Lay out a fully functional FG transistor.
You will need to use a MOS capacitor for your gate input.
Attempt extraction of this device.
Make sure all terminals are labeled; the device must be fully functional.
- Make a common-source amplifier where
the FG transistor (pFET) is the active transistor,
and an nFET transistor is the biasing current source.
You should set the nFET gate voltage with an external voltage.
Use your layout above for the FG pFET device,
layout the entire circuit,
and extract the resulting circuit.
Fill in details where your extraction is not correct.
Perform a transfer-function simulation of this circuit.
Note the resulting gain, and equate that gain to your circuit parameters, either explicit or extracted.
Transimpedance Amplifier Specific Items
You will be designing the four transistor transimpedance amplifier.
A few key points for this design:
For a particular design, you will be given
- The circuit will include a cascode transistor.
- Assume the input will be a sensor that you can approximate as a current source.
- Your circuit must be self contained, that is all signal voltages (voltage that have dc path to GND)
must be within the power supplies, 0V and 1.5V.
- You can have additional transistors if you desire to do so.
- You should assume you have a single voltage bias for Vt.
- The output load capacitance is 50fF. You can add more capacitance as required.
You need to choose your Vt for your required bias current.
You need to minimize your bias current, and how you minimize the bias current is part of your grade.
You need to measure your noise level, and minimize where possible.
You can add transistors, work with the W/L of the transistors, etc.
Don't forget your cascode transistor.
Aamplifier parameters for all teams:
- Input current range
- Output voltage swing for your input signals.
- Input load capacitance
- Input Current Range = 0.1nA to 10nA,
- Sensor capacitance 500fF
- Voltage range over current level: 800mV between 0 and 1.5V
- Output load capacitance >= 50fF
- Power = 1uW
- Bandwidth = 20kHz
Folded-Cascode Specific Items
The design is a differential input, single-ended output amplifier. Some specifications are
Gain > 30,000
- CMRR > 10000
- Input swing: must allow signals to 0V (if not, then 0 points on this parameter design).
The upper range of the signals must be at least 1.0V.
- Output swing: Must enable 1.0V swing over the 1.5V supply.
- You will assume your device is driving a 0.3pF load. You may add more capacitance as needed.
- You will use the same capacitance extraction parameters as the last project.
In addition each group will be assigned for additional specifications; these specifications will be sent by email to the class. These specifications include
Part of the grade will be on the creativity of the design, as well as how well the report is written up.
- Amplifier Bandwidth
- Slew Rate
- Noise performance
- Power dissipation
The noise measurement is input referred, that is, if one has an ideal noise voltage source, it would appear in series with either the input to the positive or negative terminal. Typically from SPICE for a noise measurement, you will get noise / rt(Hz) at the output (we are only assuming thermal noise for this project), so an approximate measurement is to divide by the lowest in-band gain (you have a given -3dB frequency, so take the lowest gain in that region) to get your input referred noise / rt(Hz).
Remember that you will need to provide all biases on chip.
Address these issues in terms of area, power, and temperature effect issues.
You will need to bias the components in your design, and you are allowed to choose one resistor (as desired for your biasing) for the design. One strong suggestion would be to use a bootstrap current source generator, and use this circuit to bias any cascode elements, if desired.
Your presentation will include the table of all specifications and what specifications you achieved with the resulting data. You need to insert your target numbers for your unique specifications (4 of them; I will check that they are correct). Of course, you need to have supporting evidence for your specifications.
Folded Cascode op-amp parameters for all teacms:
- Amplifier Bandwidth 4 kHz
- Slew Rate 300 V/us
- Noise Performance 25 nV/sqrt(Hz)
- Power Dissipation 0.5 mW