The goal of this project is to understand stability in amplifier design, as well as its implications for realistic analog design (e.g. parastic capacitors). Further, this project explicitly allows using Floating-Gate (FG) circuit techniques in the designs. You will have two designs to consider for this project. Both designs require analysis, simulation, and IC layout.

- A four-transistor trans-impedance amplifier (current in to voltage out) with voltage gain.
- A folded cascode CMOS on-chip op-amp. The output stage will require cascodes on nFET and pFET devices, but just one cascode (not a stack of two or more). The particular circuit will be a small modification from the example design shown in class. As an on-chip amplifier, you do not need to have low output impedance, because the device is typically driving capacitive loads. You will assume your device is driving a 3pF load. You are allowed to add more capacitance if helpful.

In both cases, you must demonstrate stability. You must show the step response for your amplifier connected as a unity gain amplifier. Stability is defined as Q <= 1, which is equivalent to at least 45 degrees of phase margin. For both designs, Area and Power must be calculated and minimized.

- Gain > 20,000
- CMRR > 10000
- Input swing: must allow signals to 0V (if not, then 0 points on this parameter design). The upper range of the signals must be at least 1.8V.
- Output swing: Must enable 1.8V swing over the 2.5V supply.

In addition each group will be assigned for additional specifications; these specifications will be sent by email to the class. These specifications include

- Amplifier Bandwidth
- Slew Rate
- Noise performance
- Power dissipation

The noise measurement is input referred, that is, if one has an ideal noise voltage source, it would appear in series with either the input to the positive or negative terminal. Typically from SPICE for a noise measurement, you will get noise / rt(Hz) at the output (we are only assuming thermal noise for this project), so an approximate measurement is to divide by the lowest in-band gain (you have a given -3dB frequency, so take the lowest gain in that region) to get your input referred noise / rt(Hz).

Remember that you will need to provide all biases on chip. Address these issues in terms of area, power, and temperature effect issues. You will need to bias the components in your design, and you are allowed to choose one resistor (as desired for your biasing) for the design. One strong suggestion would be to use a bootstrap current source generator, and use this circuit to bias any cascode elements, if desired.

Your presentation will include the table of all specifications and what specifications you achieved with the resulting data. You need to insert your target numbers for your unique specifications (4 of them; I will check that they are correct). Of course, you need to have supporting evidence for your specifications.

- Fundamental Paper on Noise in Transistors by Dr. Sarpeskhar (currently at MIT)
- Classic Design for an OTA-based, Low-Noise High-Gain Amplifier by Dr. Harrison.
- Bootstrap Current Reference
- Additional Notes on FPAA device

- Lecture 19: